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pcf8563 real time clock/calendar rev. 04 12 march 2004 product data 1. general description the pcf8563 is a cmos real time clock/calendar optimized for low power consumption. a programmable clock output, interrupt output and voltage-low detector are also provided. all address and data are transferred serially via a two-line bidirectional i 2 c-bus. maximum bus speed is 400 kbit/s. the built-in word address register is incremented automatically after each written or read data byte. 2. features n provides year, month, day, weekday, hours, minutes and seconds based on 32.768 khz quartz crystal n century ?ag n clock operating voltage: 1.8 v to 5.5 v n low backup current; typical 0.25 m a at v dd = 3.0 v and t amb =25 c n 400 khz two-wire i 2 c-bus interface (at v dd = 1.8 v to 5.5 v) n programmable clock output for peripheral devices (32.768 khz, 1024 hz, 32 hz and 1 hz) n alarm and timer functions n integrated oscillator capacitor n internal power-on reset n i 2 c-bus slave address: read a3h and write a2h n open-drain interrupt pin. 3. applications n mobile telephones n portable instruments n fax machines n battery powered products.
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 2 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 4. quick reference data 5. ordering information table 1: quick reference data symbol parameter conditions min typ max unit v dd supply voltage operating; i 2 c-bus inactive; t amb =25 c 1.0 - 5.5 v operating; i 2 c-bus active; f scl = 400 khz; t amb = - 40 c to +125 c 1.8 - 5.5 v i dd supply current timer and clock output disabled; f scl = 400 khz - - 800 m a timer and clock output disabled; f scl = 100 khz - - 200 m a timer and clock output disabled; f scl = 0 hz; t amb =25 c v dd = 5 v - - 550 na v dd = 2 v - - 450 na t amb ambient temperature operating - 40 - + 85 c t stg storage temperature - 65 - + 150 c table 2: ordering information type number package name description version pcf8563p dip8 plastic dual in-line package; 8 leads (300 mil) sot97-1 pcf8563t so8 plastic dual in-line package; 8 leads; body width 3.9 mm sot96-1 pcf8563ts tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 3 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. block diagram 7. pinning information 7.1 pinning fig 1. block diagram. mgm662 0 control/status 1 oscillator 32.768 khz 1 control/status 2 2 seconds/vl 3 minutes 4 hours 5 days 6 weekdays 7 months/century 8 years 9 minute alarm a hour alarm b day alarm c weekday alarm d e clkout control f timer control timer oscillator monitor voltage detector i 2 c-bus interface divider control logic address register por pcf8563 v dd clkout 1 hz osco scl sda v ss int osci 1 2 3 4 8 6 5 7 fig 2. pin con?guration dip8. fig 3. pin con?guration so8. fig 4. pin con?guration tssop8. 1 2 3 4 8 7 6 5 mce403 pcf8563p v dd clkout osco scl sda v ss int osci 1 2 3 4 8 7 6 5 mce198 pcf8563t v dd clkout osco scl sda v ss int osci 1 2 3 4 8 7 6 5 mce199 pcf8563ts v dd clkout osco scl sda v ss int osci
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 4 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.2 pin description 8. functional description the pcf8563 contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 khz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the real time clock/calender (rtc), a programmable clock output, a timer, an alarm, a voltage-low detector and a 400 khz i 2 c-bus interface. all 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. the ?rst two registers (memory address 00h and 01h) are used as control and/or status registers. the memory addresses 02h through 08h are used as counters for the clock function (seconds up to years counters). address locations 09h through 0ch contain alarm registers which de?ne the conditions for an alarm. address 0dh controls the clkout output frequency. 0eh and 0fh are the timer control and timer registers, respectively. the seconds, minutes, hours, days, weekdays, months, years as well as the minute alarm, hour alarm, day alarm and weekday alarm registers are all coded in bcd format. when one of the rtc registers is read the contents of all counters are frozen. therefore, faulty reading of the clock/calendar during a carry condition is prevented. fig 5. device diode protection diagram. handbook, halfpage mgr886 sda 4 5 v ss scl 3 6 int clkout 2 7 osco v dd 1 8 osci pcf8563 table 3: pin description symbol pin description osci 1 oscillator input osco 2 oscillator output int 3 interrupt output (open-drain; active low) v ss 4 ground sda 5 serial data input and output scl 6 serial clock input clkout 7 clock output, open-drain v dd 8 positive supply voltage
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 5 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.1 alarm function modes by clearing the msb of one or more of the alarm registers (bit ae = alarm enable), the corresponding alarm condition(s) will be active. in this way an alarm can be generated from once per minute up to once per week. the alarm condition sets the alarm flag (af). the asserted af can be used to generate an interrupt ( int). the af can only be cleared by software. 8.2 timer the 8-bit countdown timer at address 0fh is controlled by the timer control register at address 0eh. the timer control register determines one of 4 source clock frequencies for the timer (4096 hz, 64 hz, 1 hz, or 1 60 hz), and enables or disables the timer. the timer counts down from a software-loaded 8-bit binary value. at the end of every countdown, the timer sets the timer flag (tf). the tf may only be cleared by software. the asserted tf can be used to generate an interrupt ( int). the interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of tf. bit ti/tp is used to control this mode selection. when reading the timer, the current countdown value is returned. 8.3 clock output a programmable square wave is available at pin clkout. operation is controlled by the clkout control register at address 0dh. frequencies of 32.768 khz (default), 1024 hz, 32 hz and 1 hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. clkout is an open-drain output and enabled at power-on. if disabled it becomes high-impedance. 8.4 reset the pcf8563 includes an internal reset circuit which is active whenever the oscillator is stopped. in the reset state the i 2 c-bus logic is initialized and all registers, including the address pointer, are cleared with the exception of bits fe, vl, td1, td0, testc and ae which are set to logic 1. 8.5 voltage-low detector the pcf8563 has an on-chip voltage-low detector. when v dd drops below v low , bit vl in the seconds register is set to indicate that the integrity of the clock information is no longer guaranteed. the vl ?ag can only be cleared by software. bit vl is intended to detect the situation when v dd is decreasing slowly, for example under battery operation. should v dd reach v low before power is re-asserted then bit vl will be set. this will indicate that the time may be corrupted.
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 6 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.6 register organization fig 6. voltage-low detection. handbook, halfpage vl set normal power operation period of battery operation t v dd v low mgr887 table 4: binary formatted registers overview bit positions labelled as x are not implemented. bit positions labelled with 0 should always be written with logic 0; if read they could be either logic 0 or logic 1. address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h control/status 1 test1 0 stop 0 testc 0 0 0 01h control/status 2 0 0 0 ti/tp af tf aie tie 0dh clkout control fe xxxxxfd1fd0 0eh timer control te xxxxxtd1td0 0fh timer table 5: bcd formatted registers overview bit positions labelled as x are not implemented. address register name bcd format tens nibble bcd format units nibble bit 7 2 3 bit 6 2 2 bit 5 2 1 bit 4 2 0 bit 3 2 3 bit 2 2 2 bit 1 2 1 bit 0 2 0 02h seconds vl 03h minutes x 04h hours x x 05h days x x 06h weekdays xxxxx 07h months/century c x x 08h years 09h minute alarm ae 0ah hour alarm ae x 0bh day alarm ae x 0ch weekday alarm ae xxxx
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 7 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.6.1 control/status 1 register 8.6.2 control/status 2 register bits tf and af: when an alarm occurs, af is set to 1. similarly, at the end of a timer countdown, tf is set to 1. these bits maintain their value until overwritten by software. if both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bits. to prevent one ?ag being overwritten while clearing another a logic and is performed during a write access. bits tie and aie: these bits activate or deactivate the generation of an interrupt when tf or af is asserted, respectively. the interrupt is the logical or of these two conditions when both aie and tie are set. table 6: control/status 1 (address 00h) bits description bit symbol value description 7 test1 0 normal mode 1 ext_clk test mode 6 0 default value is logic 0 5 stop 0 rtc source clock runs 1 all rtc divider chain ?ip-?ops are asynchronously set to logic 0; the rtc clock is stopped (clkout at 32.768 khz is still available) 4 0 default value is logic 0 3 testc 0 power-on reset override facility is disabled; set to logic 0 for normal operation 1 power-on reset override may be enabled 2 to 0 0 default value is logic 0 table 7: control/status 2 (address 01h) bits description bit symbol value description 7 to 5 0 default value is logic 0 4 ti/tp 0 int is active when tf is active (subject to the status of tie) 1 int pulses active according to ta b l e 8 (subject to the status of tie); note that if af and aie are active then int will be permanently active 3 af 0 (read) alarm ?ag inactive 1 (read) alarm ?ag active 0 (write) alarm ?ag is cleared 1 (write) alarm ?ag remains unchanged 2 tf 0 (read) timer ?ag inactive 1 (read) timer ?ag active 0 (write) timer ?ag is cleared 1 (write) timer ?ag remains unchanged 1 aie 0 alarm interrupt disabled 1 alarm interrupt enabled 0 tie 0 timer interrupt disabled 1 timer interrupt enabled
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 8 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] tf and int become active simultaneously. [2] n = loaded countdown value. timer stopped when n = 0. 8.6.3 time and date registers [1] the pcf8563 compensates for leap years by adding a 29th day to february if the year counter contains a value which is exactl y divisible by 4, including the year 00. [1] these bits may be re-assigned by the user. table 8: int operation (bit ti/tp = 1) source clock (hz) int period (s) [1] n=1 [2] n>1 4 096 1 8192 1 4096 64 1 128 1 64 1 1 64 1 64 1 60 1 64 1 64 table 9: seconds/vl (address 02h) bits description bit symbol value description 7 vl 0 clock integrity is guaranteed 1 integrity of the clock information is no longer guaranteed 6 to 0 seconds 00 to 59 this register holds the current seconds coded in bcd format; example: seconds register contains x101 1001 = 59 seconds table 10: minutes (address 03h) bits description bit symbol value description 6 to 0 minutes 00 to 59 this register holds the current minutes coded in bcd format table 11: hours (address 04h) bits description bit symbol value description 5 to 0 hours 00 to 23 this register holds the current hours coded in bcd format table 12: days (address 05h) bits description bit symbol value description 5 to 0 days [1] 01 to 31 this register holds the current day coded in bcd format table 13: weekdays (address 06h) bits description bit symbol value description 2 to 0 weekdays [1] 0 to 6 this register holds the current weekday coded in bcd format, see ta b l e 1 4 table 14: weekday assignments day bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sunday xxxxx000 monday xxxxx001 tuesday xxxxx010 wednesday xxxxx011
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 9 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] these bits may be re-assigned by the user. 8.6.4 alarm registers when one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit alarm enable (ae) is logic 0, then that information will be compared with the current minute, hour, day and weekday. when all enabled comparisons ?rst match, the alarm flag (af) is set. af will remain set until cleared by software. once af has been cleared it will only be set again when the time increments to match the alarm condition once more. alarm registers which have their bit ae at logic 1 will be ignored. thursday xxxxx100 friday xxxxx101 saturday xxxxx110 table 14: weekday assignments continued day bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 15: months/century (address 07h) bits description bit symbol value description 7 century [1] this bit is toggled when the years register over?ows from 99 to 00 0 indicates the century is 20xx 1 indicates the century is 19xx 4 to 0 month 01 to 12 this register holds the current month coded in bcd format, see ta bl e 1 6 table 16: month assignments month bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 january cxx00001 february cxx00010 march c x x 00011 april cxx00100 may cxx00101 june cxx00110 july cxx00111 august c x x 01000 september c x x 01001 october c x x 10000 november c x x 10001 december c x x 10010 table 17: years (address 08h) bits description bit symbol value description 7 to 0 years 00 to 99 this register holds the current year coded in bcd format
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 10 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.6.5 clock output control register 8.6.6 countdown timer the timer register is an 8-bit binary countdown timer. it is enabled and disabled via the timer control register bit te. the source clock for the timer is also selected by the timer control register. other timer properties such as interrupt generation are controlled via control/status 2 register. table 18: minute alarm (address 09h) bits description bit symbol value description 7 ae 0 minute alarm is enabled 1 minute alarm is disabled 6 to 0 alarm minutes 00 to 59 this register holds the minute alarm information coded in bcd format table 19: hour alarm (address 0ah) bits description bit symbol value description 7 ae 0 hour alarm is enabled 1 hour alarm is disabled 5 to 0 alarm hours 00 to 23 this register holds the hour alarm information coded in bcd format table 20: day alarm (address 0bh) bits description bit symbol value description 7 ae 0 day alarm is enabled 1 day alarm is disabled 5 to 0 alarm days 01 to 31 this register holds the day alarm information coded in bcd format table 21: weekday alarm (address 0ch) bits description bit symbol value description 7 ae 0 weekday alarm is enabled 1 weekday alarm is disabled 2 to 0 alarm weekdays 0 to 6 this register holds the weekday alarm information coded in bcd format table 22: clkout control (address 0dh) bits description bit symbol value description 7 fe 0 the clkout output is inhibited and clkout output is set to high-impedance 1 the clkout output is activated 1 to 0 fd1 and fd0 these bits control the frequency output at pin clkout; see ta b l e 2 3 table 23: fd1 and fd0: clkout frequency selection fd1 fd0 clkout frequency 0 0 32.768 khz 0 1 1024 hz 1032hz 111hz
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 11 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. for accurate read back of the countdown value, the i 2 c-bus clock (scl) must be operating at a frequency of at least twice the selected timer clock. 8.7 ext_clk test mode a test mode is available which allows for on-board testing. in such a mode it is possible to set up test conditions and control the operation of the rtc. the test mode is entered by setting bit test1 in control/status1 register. then pin clkout becomes an input. the test mode replaces the internal 64 hz signal with the signal applied to pin clkout. every 64 positive edges applied to pin clkout will then generate an increment of one second. the signal applied to pin clkout should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. the internal 64 hz clock, now sourced from clkout, is divided down to 1 hz by a 2 6 divide chain called a pre-scaler. the pre-scaler can be set into a known state by using bit stop. when bit stop is set, the pre-scaler is reset to 0 (stop must be cleared before the pre-scaler can operate again). from a stop condition, the ?rst 1 second increment will take place after 32 positive edges on clkout. thereafter, every 64 positive edges will cause a 1 second increment. remark: entry into ext_clk test mode is not synchronized to the internal 64 hz clock. when entering the test mode, no assumption as to the state of the pre-scaler can be made. operation example: 1. set ext_clk test mode (control/status 1, bit test1 = 1) 2. set stop (control/status 1, bit stop = 1) table 24: timer control (address 0eh) bits description bit symbol value description 7 te 0 timer is disabled 1 timer is enabled 1 to 0 td1 and td0 timer source clock frequency select; these bits determine the source clock for the countdown timer, see ta b l e 2 5 ; when not in use, td1 and td0 should be set to 1 60 hz for power saving table 25: td1 and td0: timer frequency selection td1 td0 timer source clock frequency 0 0 4096 hz 0164hz 101hz 11 1 60 hz table 26: timer (address 0fh) bits description bit symbol value description 7 to 0 timer 00 to ff countdown value = n; countdownperiod n sourceclockfrequency -------------------------------------------------------------- - =
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 12 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 3. clear stop (control/status 1, bit stop = 0) 4. set time registers to desired value 5. apply 32 clock pulses to clkout 6. read time registers to see the ?rst change 7. apply 64 clock pulses to clkout 8. read time registers to see the second change. repeat 7 and 8 for additional increments. 8.8 power-on reset (por) override the por duration is directly related to the crystal oscillator start-up time. due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the por and hence speed up on-board test of the device. the setting of this mode requires that the i 2 c-bus pins, sda and scl, be toggled in a speci?c order as shown in figure 7 . all timings are required minimums. once the override mode has been entered, the device immediately stops being reset and normal operation may commence i.e. entry into the ext_clk test mode via i 2 c-bus access. the override mode may be cleared by writing a logic 0 to testc. testc must be set to logic 1 before re-entry into the override mode is possible. setting testc to logic 0 during normal operation has no effect except to prevent entry into the por override mode. 9. characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 9.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 8 ). fig 7. por override sequence. handbook, full pagewidth mgm664 scl 500 ns 2000 ns sda 8 ms override active power up
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 13 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is de?ned as the start condition (s). a low-to-high transition of the data line while the clock is high is de?ned as the stop condition (p); see figure 9 . 9.3 system con?guration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 10 ). 9.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high-level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related fig 8. bit transfer. mbc621 data line stable; data valid change of data allowed sda scl fig 9. de?nition of start and stop conditions. mbc622 sda scl p stop condition sda scl s start condition fig 10. system con?guration. mba605 master transmitter / receiver slave receiver slave transmitter / receiver master transmitter master transmitter / receiver sda scl
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 14 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. 9.5 i 2 c-bus protocol 9.5.1 addressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed ?rst. the addressing is always carried out with the ?rst byte transmitted after the start procedure. the pcf8563 acts as a slave receiver or slave transmitter. therefore the clock signal scl is only an input signal, but the data signal sda is a bidirectional line. the pcf8563 slave address is shown in figure 12 . fig 11. acknowledgement on the i 2 c-bus. mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master fig 12. slave address. mce189 1 0 1 0 0 0 1 r/w group 1 group 2
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 15 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.5.2 clock/calendar read/write cycles the i 2 c-bus con?guration for the different pcf8563 read and write cycles is shown in figure 13 , figure 14 and figure 15 . the word address is a 4-bit value that de?nes which register is to be accessed next. the upper four bits of the word address are not used. fig 13. master transmits to slave receiver (write mode). s 0a slave address word address a a data p acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w auto increment memory word address mbd822 n bytes fig 14. master reads after setting word address (write word address; read data). s 0a slave address word address a a slave address acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w acknowledgement from master a data auto increment memory word address mce172 p no acknowledgement from master 1 data auto increment memory word address last byte r/w s1 n bytes at this moment master transmitter becomes master receiver and pca8565 slave receiver becomes slave transmitter fig 15. master reads slave immediately after ?rst byte (read mode). handbook, full pagewidth s 1a slave address data a1 data acknowledgement from slave acknowledgement from master no acknowledgement from master r/w auto increment word address mgl665 auto increment word address n bytes last byte p
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 16 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. limiting values 11. static characteristics table 27: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter min max unit v dd supply voltage - 0.5 +6.5 v i dd supply current - 50 +50 ma v i input voltage on pins scl and sda - 0.5 +6.5 v input voltage on pin osci - 0.5 v dd + 0.5 v v o output voltage on pins clockout and int - 0.5 +6.5 v i i dc input current at any input - 10 +10 ma i o dc output current at any output - 10 +10 ma p tot total power dissipation - 300 mw t amb ambient temperature - 40 +85 c t stg storage temperature - 65 +150 c table 28: static characteristics v dd = 1.8 v to 5.5 v; v ss =0v; t amb = - 40 c to +85 c; f osc = 32.768 khz; quartz r s =40k w ; c l = 8 pf; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dd supply voltage interface inactive; t amb =25 c [1] 1.0 - 5.5 v interface active; f scl = 400 khz [1] 1.8 - 5.5 v v dd(clock) supply voltage for clock data integrity t amb =25 cv low - 5.5 v i dd1 supply current 1 interface active f scl = 400 khz - - 800 m a f scl = 100 khz - - 200 m a i dd2 supply current 2 interface inactive (f scl = 0 hz); clkout disabled; t amb =25 c [2] v dd = 5.0 v - 275 550 na v dd = 3.0 v - 250 500 na v dd = 2.0 v - 225 450 na interface inactive (f scl = 0 hz); clkout disabled; t amb = - 40 to +85 c [2] v dd = 5.0 v - 500 750 na v dd = 3.0 v - 400 650 na v dd = 2.0 v - 400 600 na
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 17 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] for reliable oscillator start-up at power-up: v dd(min)power-up =v dd(min) + 0.3 v. [2] timer source clock = 1 60 hz, level of pins scl and sda is v dd or v ss . [3] tested on sample basis. i dd3 supply current 3 interface inactive (f scl = 0 hz); clkout enabled at 32 khz; t amb =25 c [2] v dd = 5.0 v - 825 1600 na v dd = 3.0 v - 550 1000 na v dd = 2.0 v - 425 800 na interface inactive (f scl = 0 hz); clkout enabled at 32 khz; t amb = - 40 to +85 c [2] v dd = 5.0 v - 950 1700 na v dd = 3.0 v - 650 1100 na v dd = 2.0 v - 500 900 na inputs v il low-level input voltage v ss - 0.3v dd v v ih high-level input voltage 0.7v dd -v dd v i li input leakage current v i =v dd or v ss - 10 +1 m a c i input capacitance [3] --7pf outputs i ol(sda) sda low-level output current v ol = 0.4 v; v dd =5v - 3- - ma i ol( int) int low-level output current v ol = 0.4 v; v dd =5v - 1- - ma i ol(clkout) clkout low-level output current v ol = 0.4 v; v dd =5v - 1- - ma i oh(clkout) clkout high-level output current v oh = 4.6 v; v dd =5v 1 - - ma i lo output leakage current v o =v dd or v ss - 10 +1 m a voltage detector v low low voltage detection t amb =25 c - 0.9 1.0 v table 28: static characteristics continued v dd = 1.8 v to 5.5 v; v ss =0v; t amb = - 40 c to +85 c; f osc = 32.768 khz; quartz r s =40k w ; c l = 8 pf; unless otherwise speci?ed. symbol parameter conditions min typ max unit
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 18 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. dynamic characteristics [1] unspeci?ed for f clkout = 32.768 khz. [2] all timing values are valid within the operating supply voltage at ambient temperature and referenced to v il and v ih with an input voltage swing of v ss to v dd . [3] a detailed description of the i 2 c-bus speci?cation, with applications, is given in brochure the i 2 c-bus and how to use it . this brochure may be ordered using the code 9398 393 40011. [4] i 2 c-bus access time between two starts or between a start and a stop condition to this device must be less than one second. table 29: dynamic characteristics v dd = 1.8 v to 5.5 v; v ss =0v; t amb = - 40 c to +85 c; f osc = 32.768 khz; quartz r s =40k w ; c l = 8 pf; unless otherwise speci?ed. symbol parameter conditions min typ max unit oscillator c int integrated load capacitance 15 25 35 pf d f osc /f osc oscillator stability d v dd = 200 mv; t amb =25 c- 2 10 -7 -- quartz crystal parameters (f = 32.768 khz) r s series resistance - - 40 k w c l parallel load capacitance - 10 - pf c t trimmer capacitance 5 - 25 pf clkout output d clkout clkout duty cycle [1] -50-% i 2 c-bus timing characteristics [2][3] f scl scl clock frequency [4] - - 400 khz t hd;sta start condition hold time 0.6 - - m s t su;sta set-up time for a repeated start condition 0.6 - - m s t low scl low time 1.3 - - m s t high scl high time 0.6 - - m s t r scl and sda rise time - - 0.3 m s t f scl and sda fall time - - 0.3 m s c b capacitive bus line load - - 400 pf t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns t su;sto set-up time for stop condition 0.6 - - m s t sw tolerable spike width on bus --50ns
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 19 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 16. i 2 c-bus timing waveforms. sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat t amb =25 c; timer = 1 minute. t amb =25 c; timer = 1 minute. fig 17. i dd as a function of v dd ; clkout disabled. fig 18. i dd as a function of v dd ; clkout = 32 khz. handbook, halfpage 02 6 mgr888 4 v dd (v) 1 0 0.4 0.2 0.8 0.6 i dd ( m a) handbook, halfpage 02 6 mgr889 4 v dd (v) 1 0 0.4 0.2 0.8 0.6 i dd ( m a)
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 20 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. application information v dd = 3 v; timer = 1 minute. t amb =25 c; normalized to v dd =3v. fig 19. i dd as a function of t; clkout = 32 khz. fig 20. frequency deviation as a function of v dd . handbook, halfpage - 40 0 40 120 mgr890 80 t ( c) 1 0 0.4 0.2 0.8 0.6 i dd ( m a) handbook, halfpage 02 6 4 2 - 4 - 2 0 mgr891 4 v dd (v) frequency deviation (ppm) fig 21. application diagram. handbook, full pagewidth mgm665 scl sda v ss osci osco clock calendar pcf8563 sda scl master transmitter/ receiver v dd v dd sda scl rr v dd (i 2 c-bus) r: pull-up resistor r = 1 f t r c b
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 21 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.1 quartz frequency adjustment 13.1.1 method 1: ?xed osci capacitor by evaluating the average capacitance necessary for the application layout, a ?xed capacitor can be used. the frequency is best measured via the 32.768 khz signal available after power-on at pin clkout. the frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 5 10 - 6 ). average deviations of 5 minutes per year can be easily achieved. 13.1.2 method 2: osci trimmer using the 32.768 khz signal available after power-on at pin clkout, fast setting of a trimmer is possible. 13.1.3 method 3: osco output direct measurement of osco out (accounting for test probe capacitance).
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 22 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. package outline fig 22. package outline sot97-1. references outline version european projection issue date iec jedec jeita sot97-1 99-12-27 03-02-13 unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.14 0.53 0.38 0.36 0.23 9.8 9.2 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 1.15 4.2 0.51 3.2 inches 0.068 0.045 0.021 0.015 0.014 0.009 1.07 0.89 0.042 0.035 0.39 0.36 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.045 0.17 0.02 0.13 b 2 050g01 mo-001 sc-504-8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 8 1 5 4 b e 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. pin 1 index dip8: plastic dual in-line package; 8 leads (300 mil) sot97-1
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 23 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 23. package outline sot96-1. unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 99-12-27 03-02-18
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 24 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 24. package outline sot505-1. unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.70 0.35 6 0 0.1 0.1 0.1 0.94 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.4 sot505-1 99-04-09 03-02-18 w m b p d z e 0.25 14 8 5 q a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 1.1 pin 1 index
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 25 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15. soldering 15.1 introduction this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. 15.2 through-hole mount packages 15.2.1 soldering by dipping or by solder wave typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the speci?ed maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.2.2 manual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 15.3 surface mount packages 15.3.1 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all the bga and ssop-t packages
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 26 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3.2 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 15.3.3 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 27 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15.4 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [4] hot bar soldering or manual soldering is suitable for pmfp packages. [5] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [6] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [7] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [8] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [9] wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. table 30: suitability of ic packages for wave, re?ow and dipping soldering methods mounting package [1] soldering method wave re?ow [2] dipping through-hole mount dbs, dip, hdip, rdbs, sdip, sil suitable [3] - suitable through-hole- surface mount pmfp [4] not suitable not suitable - surface mount bga, lbga, lfbga, sqfp, ssop-t [5] , tfbga, vfbga not suitable suitable - dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable [6] suitable - plcc [7] , so, soj suitable suitable - lqfp, qfp, tqfp not recommended [7][8] suitable - ssop, tssop, vso, vssop not recommended [9] suitable -
philips semiconductors pcf8563 real time clock/calendar product data rev. 04 12 march 2004 28 of 30 9397 750 12999 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16. revision history table 31: revision history rev date cpcn description 04 20040312 - product data (9397 750 12999) modi?cations: ? corrections in the unit column of ta b l e 1 . 03 20030414 - product data (9397 750 11158) 02 19990416 - product data (9397 750 04855)
9397 750 12999 philips semiconductors pcf8563 real time clock/calendar ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 12 march 2004 29 of 30 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 17. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 19. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 20. licenses level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c speci?cation de?ned by philips. this speci?cation can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 12 march 2004 document order number: 9397 750 12999 contents philips semiconductors pcf8563 real time clock/calendar 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 4 8.1 alarm function modes. . . . . . . . . . . . . . . . . . . . 5 8.2 timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.3 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.5 voltage-low detector . . . . . . . . . . . . . . . . . . . . . 5 8.6 register organization . . . . . . . . . . . . . . . . . . . . 6 8.6.1 control/status 1 register . . . . . . . . . . . . . . . . . . 7 8.6.2 control/status 2 register . . . . . . . . . . . . . . . . . . 7 8.6.3 time and date registers . . . . . . . . . . . . . . . . . . 8 8.6.4 alarm registers . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.6.5 clock output control register . . . . . . . . . . . . . . 10 8.6.6 countdown timer. . . . . . . . . . . . . . . . . . . . . . . 10 8.7 ext_clk test mode . . . . . . . . . . . . . . . . . . . . 11 8.8 power-on reset (por) override . . . . . . . . . . 12 9 characteristics of the i 2 c-bus. . . . . . . . . . . . . 12 9.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9.2 start and stop conditions . . . . . . . . . . . . . . . . 13 9.3 system con?guration . . . . . . . . . . . . . . . . . . . 13 9.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 13 9.5 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 14 9.5.1 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.5.2 clock/calendar read/write cycles . . . . . . . . . . 15 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 11 static characteristics. . . . . . . . . . . . . . . . . . . . 16 12 dynamic characteristics . . . . . . . . . . . . . . . . . 18 13 application information. . . . . . . . . . . . . . . . . . 20 13.1 quartz frequency adjustment . . . . . . . . . . . . . 21 13.1.1 method 1: ?xed osci capacitor . . . . . . . . . . . 21 13.1.2 method 2: osci trimmer. . . . . . . . . . . . . . . . . 21 13.1.3 method 3: osco output . . . . . . . . . . . . . . . . . 21 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 15 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 25 15.2 through-hole mount packages . . . . . . . . . . . . 25 15.2.1 soldering by dipping or by solder wave . . . . . 25 15.2.2 manual soldering . . . . . . . . . . . . . . . . . . . . . . 25 15.3 surface mount packages . . . . . . . . . . . . . . . . 25 15.3.1 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 25 15.3.2 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 26 15.3.3 manual soldering . . . . . . . . . . . . . . . . . . . . . . 26 15.4 package related soldering information . . . . . . 27 16 revision history . . . . . . . . . . . . . . . . . . . . . . . 28 17 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 29 18 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 19 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 20 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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